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@@ -459,7 +459,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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case LogicalOperation.ExclusiveOr: res = context.BitwiseExclusiveOr(srcA, srcB); break;
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}
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- EmitLopPredWrite(context, op, res);
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+ EmitLopPredWrite(context, op, res, (ConditionalOperation)context.CurrOp.RawOpCode.Extract(44, 2));
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Operand dest = GetDest(context);
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@@ -486,7 +486,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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if (regVariant)
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{
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- EmitLopPredWrite(context, op, res);
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+ EmitLopPredWrite(context, op, res, (ConditionalOperation)context.CurrOp.RawOpCode.Extract(36, 2));
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}
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Operand dest = GetDest(context);
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@@ -917,21 +917,21 @@ namespace Ryujinx.Graphics.Shader.Instructions
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return res;
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}
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- private static void EmitLopPredWrite(EmitterContext context, IOpCodeLop op, Operand result)
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+ private static void EmitLopPredWrite(EmitterContext context, IOpCodeLop op, Operand result, ConditionalOperation condOp)
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{
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if (op is OpCodeLop opLop && !opLop.Predicate48.IsPT)
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{
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Operand pRes;
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- if (opLop.CondOp == ConditionalOperation.False)
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+ if (condOp == ConditionalOperation.False)
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{
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pRes = Const(IrConsts.False);
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}
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- else if (opLop.CondOp == ConditionalOperation.True)
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+ else if (condOp == ConditionalOperation.True)
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{
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pRes = Const(IrConsts.True);
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}
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- else if (opLop.CondOp == ConditionalOperation.Zero)
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+ else if (condOp == ConditionalOperation.Zero)
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{
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pRes = context.ICompareEqual(result, Const(0));
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}
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