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@@ -2426,7 +2426,11 @@ namespace ARMeilleure.Instructions
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}
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else if (Optimizations.FastFP && Optimizations.UseSse41 && sizeF == 0)
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{
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- Operand res = EmitSse41Round32Exp8OpF(context, context.AddIntrinsic(Intrinsic.X86Rsqrtss, GetVec(op.Rn)), scalar: true);
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+ // RSQRTSS handles subnormals as zero, which differs from Arm, so we can't use it here.
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+
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+ Operand res = context.AddIntrinsic(Intrinsic.X86Sqrtss, GetVec(op.Rn));
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+ res = context.AddIntrinsic(Intrinsic.X86Rcpss, res);
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+ res = EmitSse41Round32Exp8OpF(context, res, scalar: true);
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context.Copy(GetVec(op.Rd), context.VectorZeroUpper96(res));
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}
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@@ -2451,7 +2455,11 @@ namespace ARMeilleure.Instructions
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}
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else if (Optimizations.FastFP && Optimizations.UseSse41 && sizeF == 0)
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{
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- Operand res = EmitSse41Round32Exp8OpF(context, context.AddIntrinsic(Intrinsic.X86Rsqrtps, GetVec(op.Rn)), scalar: false);
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+ // RSQRTPS handles subnormals as zero, which differs from Arm, so we can't use it here.
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+
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+ Operand res = context.AddIntrinsic(Intrinsic.X86Sqrtps, GetVec(op.Rn));
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+ res = context.AddIntrinsic(Intrinsic.X86Rcpps, res);
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+ res = EmitSse41Round32Exp8OpF(context, res, scalar: false);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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