Fix CPU FCVTN instruction implementation (slow path) (#4159)

* Fix CPU FCVTN instruction implementation (slow path)

* PPTC version bump

ARMeilleure/Instructions/InstEmitSimdCvt.cs

@@ -381,7 +381,7 @@ namespace ARMeilleure.Instructions
 
                 for (int index = 0; index < elems; index++)
                 {
-                    Operand ne = context.VectorExtract(type, GetVec(op.Rn), 0);
+                    Operand ne = context.VectorExtract(type, GetVec(op.Rn), index);
 
                     if (sizeF == 0)
                     {
@@ -389,8 +389,6 @@ namespace ARMeilleure.Instructions
                         Operand e = context.Call(typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert)), ne);
                         context.LoadFromContext();
 
-                        e = context.ZeroExtend16(OperandType.I64, e);
-
                         res = EmitVectorInsert(context, res, e, part + index, 1);
                     }
                     else /* if (sizeF == 1) */

ARMeilleure/Translation/PTC/Ptc.cs

@@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
         private const string OuterHeaderMagicString = "PTCohd\0\0";
         private const string InnerHeaderMagicString = "PTCihd\0\0";
 
-        private const uint InternalVersion = 4140; //! To be incremented manually for each change to the ARMeilleure project.
+        private const uint InternalVersion = 4159; //! To be incremented manually for each change to the ARMeilleure project.
 
         private const string ActualDir = "0";
         private const string BackupDir = "1";

Ryujinx.Tests/Cpu/CpuTestSimd.cs

@@ -2176,8 +2176,8 @@ namespace Ryujinx.Tests.Cpu
             opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
             opcodes |= ((q & 1) << 30);
 
-            V128 v0 = MakeVectorE0E1(z, z);
-            V128 v1 = MakeVectorE0E1(a, a);
+            V128 v0 = MakeVectorE0E1(z, a);
+            V128 v1 = MakeVectorE0E1(a, z);
 
             int rnd = (int)TestContext.CurrentContext.Random.NextUInt();
 
@@ -2202,8 +2202,8 @@ namespace Ryujinx.Tests.Cpu
             opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
             opcodes |= ((q & 1) << 30);
 
-            V128 v0 = MakeVectorE0E1(z, z);
-            V128 v1 = MakeVectorE0E1(a, a);
+            V128 v0 = MakeVectorE0E1(z, a);
+            V128 v1 = MakeVectorE0E1(a, z);
 
             SingleOpcode(opcodes, v0: v0, v1: v1);